dorsaVi Advances 22nm RRAM Development With CMOS Validation Chip Tape-Out

dorsaVi (ASX: DVL) has begun the tape-out process for its first resistive random-access memory (RRAM) and complementary metal-oxide-semiconductor (CMOS) validation chip, moving its 22-nanometre (22nm) development program from completed design towards physical silicon manufacturing.

The milestone advances the chip into the implementation flow needed to fabricate silicon for wafer-level electrical testing under commercial foundry conditions.

The staged process uses commercial CMOS front-end wafers followed by partner-led back-end-of-line and RRAM integration before electrical testing begins.

The chip is designed to generate data on memory array operation, write-and-verify behaviour, compute-in-memory (CIM) functionality, sensing, and process performance for potential AI, robotics, defence, medical, and wearable applications.

The validation work supports dorsaVi’s broader ultra-edge intelligence roadmap, which combines local memory, low-power processing, and on-device decisions for sensing and hardware platforms operating under energy, response-time, or connectivity constraints.

Testing Targets Core Functions

Physical silicon testing will assess whether the RRAM memory macro, peripheral circuits, write-and-verify function, sensing paths, and CIM structures operate together as intended.

The architecture places computation within the memory array so the same physical layer can store data and perform calculations locally, reducing the need to move information repeatedly between separate memory and processing components.

dorsaVi plans to measure circuit speed, read access times, CIM performance, and overall array-level behaviour while examining resistance-state separation, sensing margins, and memory readout performance.

The resulting silicon data is expected to guide RRAM integration, circuit optimisation, manufacturing refinement, and the planned progression of the 22nm platform.

Potential Commercial Pathways

dorsaVi has identified two potential commercial pathways, involving direct integration into end devices and collaboration with foundries and fabless chip makers on specialised products.

Compatibility with commercial CMOS front-end wafers and established BEOL processes is designed to support manufacturing through existing foundry infrastructure rather than requiring an entirely new production platform.

The staged implementation approach will seek to preserve flexibility for process learning, electrical test development, and future migration while evaluating RRAM integration on a commercial CMOS foundation.

Wafer-level electrical testing will follow fabrication and integration, with the results intended to inform further optimisation and the next stage of 22nm RRAM-CMOS development.

Target Market Applications

Target markets include smart exoskeletons, robotics, autonomous defence sensing, industrial AI, medical wearables and electric vehicles, where local low-power memory could support on-device decision-making without constant cloud connectivity.

For exoskeletons and robotics, dorsaVi is targeting functions including intent recognition, joint positioning, and torque control using memory that retains data through power cycles.

Defence and industrial applications could use local inference for autonomous edge sensing and model processing, while medical wearables could retain patient baselines for continuous biosignal monitoring.

“Commencing the tape-out of our first RRAM test-chip […] confirms that our RRAM architecture is manufacturable under standard commercial foundry conditions and gives us the physical silicon we need to validate performance and refine the technology," group chief executive officer Mathew Regan said.

“We are focused on executing this next phase of testing and using the results to advance the program toward commercial scaling.”